interface aru_arb_rdgen_cfg_pipe_crd_gen_if (
    input clk,
    input rst_n
);
    logic vld;
    logic rdy;
    idx_t slice_m;
    idx_t slice_n;
    logic reduce_m;
    modport in(input vld, input slice_m, input slice_n, input reduce_m, output rdy);
    modport out(output vld, output slice_m, output slice_n, output reduce_m, input rdy);
endinterface

interface aru_arb_rdgen_cfg_pipe_if (
    input clk,
    input rst_n
);
    logic vld;
    logic rdy;
    idx_t slice_m;
    idx_t slice_n;
    logic reduce_m;
    modport in(input vld, input slice_m, input slice_n, input reduce_m, output rdy);
    modport out(output vld, output slice_m, output slice_n, output reduce_m, input rdy);
endinterface
